As device size scales downwardly for devices such as metal oxide field effect transistors (MOSFET) including complementary metal oxide semiconductors (CMOS), a factor limiting device performance is parasitic resistance, which includes contact resistance between metal contact to the source/drain (S/D) regions of the device. The contact resistance Rc is characterized by a specific contact resistivity or contact resistivity ρc in units of Ωcm2.
In typical CMOS devices, including both p-type field effect transistors (pFET) and n-type field effect transistors (nFET), S/D contacts are created by forming a metal contact such as a silicide on top of a source/drain region. In conventional approaches, the silicide contact is formed on a silicon region that is previously implanted to a desired level with dopant species such as phosphorous (P) or Arsenic (As) in the case of nFETs and boron (B) in the case of pFETs. In a typical “salicide” process for forming a silicide, a precursor metal such as Ni, Ti, Co, Pt, or an alloy of such metal materials is deposited upon the semiconductor source/drain region, after which an annealing process is conducted to react the precursor metal to form a metal silicide by solid state interdiffusion between the semiconductor source drain and metal. The contact resistance of the silicide contact thus formed depends in part on the level of active dopants in the source/drain region proximate the silicide/semiconductor interface. One alternative approach that has recently been used to attempt to lower contact resistance is to perform room temperature implantation of dopant species through a silicide contact layer after the silicide has been formed. After room temperature implantation, annealing of the implanted substrate is performed to activate dopants and drive the dopants toward the silicide/semiconductor interface.
The above approaches each suffer from certain drawbacks. Firstly, in the case of room temperature implantation through silicide dopant clustering may take place which adversely impacts active dopant concentration at the silicide/semiconductor interface and thereby produces a higher than ideal contact resistance. Secondly, the room temperature implantation through silicide incurs an extra annealing step in order to properly activate the dopants implanted through silicide. In the approach in which the S/D region is highly doped before silicide formation, the process of silicide formation may adversely affect the desired distribution of active dopants at the silicide/semiconductor interface, also resulting in a lower than desired concentration of active dopants. It is with respect to these and other considerations that the present improvements have been needed.